The present invention relates generally to the electrical, electronic and computer arts and, more particularly, to vertical transistor structures.
Metal oxide semiconductor field-effect transistors (MOSFETs) include gate electrodes that are electrically insulated from operatively associated semiconductor channels by thin layers of dielectric material. MOSFETs having n-doped source and drain regions employ electrons as the primary current carriers while those having p-doped source and drain regions use holes as primary current carriers. Vertical transport field-effect transistors (VTFETs) have configurations wherein the current between the drain and source regions is substantially normal to the surface of the die. A vertical transport field-effect transistor may, for example, include a semiconductor pillar or fin having top and bottom regions comprising source/drain regions, the portion of the pillar between the source/drain regions defining a channel region.
Vertical transport FETs (VTFETs) are a promising alternative to standard lateral FET structures due to potential benefits, among others, in terms of reduced circuit footprint. A logic circuit comprising VTFETs can be referred to as a “vertical transport logic gate.” VTFETs can potentially provide electronic devices comprising logic circuits with improved circuit density. Such logic circuits can be characterized by a lower-number CPP (cell gate pitch) versus comparable logic circuits comprising lateral FET layouts. Minimum wiring pitch can also be relevant for realizing denser vertical FET layouts. The growth of silicon nitride and other encapsulation layers during the fabrication of vertical transport field-effect transistors (VTFETs) can impair the reliability of such transistors.